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Welcome to the Advanced Microelectronics System Design Web site [General Information] [Topology] [System Setup] [Lab Materials] [Links] |
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Mentor Graphics design toolset is one of the
primary industry EAD tools. Extensive efforts are needed to master such
comprehensive and powerful tools. Here we developed several lab materials
for students to get familiar with this software, including schematic
design, AMS simulation, layout design, design rules checking (DRC), Layout
versus schematic (LVS), Parasitic extraction (PEX), postlayout simulation,
synthesizing, design for test (DFT), ADK design, pad and frame, and how to
prepare files for MOSIS fabrication. These materials will provide you the
complete hands-on experience for the IC design flow. We will send our
designed chips to MOSIS for fabrications, and the students are responsible
for chip testing and report to MOSIS after they receive the chips from
MOSIS. Also, we provide many useful documents and Web links to help the
learning process.
Before you try to do the labs, please make sure that you already have properly set up the requirements !!! |
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(Under development - coming soon!) Lab 1: Design Architect and AMS simulation Lab 2: Layout design using IC Station Lab 3: DRC, LVS, PEX and post-layout simulation Lab 4: Synthesis and Timing Simulation Lab 5: DFT Advisor Lab 6: Automatic BIST Insertion to HDL Code Lab 7: ASIC Design Flow Lab 8: Chip design and fabrication preparation (by MOSIS) |
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Fabrication information |
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Our designed chips will be submitted to
MOSIS (California) for
fabrication through the
MOSIS Educational Program (MEP). In order to meet the
MOSIS fabrication schedule, please follow exactly the project timeline
and test your design extensively!!!
We will use ASIC Design Kit (ADK 3.1) and Mentor Graphics tools to prepare design files for fabrication. The ADK enables automatically generating a TinyChip padframe for fabrication through MOSIS. Basically, after you finished your chip design and post-layout simulation (please carefully verify your simulations!!!), you need to do the following steps before submission to MOSIS: (1) Prepare a top-level layout to contain the design inside a padframe. (2) Add Padframe and generate the layout (3) Generate fabrication data (GDSII file) The detailed instruction is in the user manual Chapter 5. After you generated the GDSII file, the TA will submit the design to MOSIS for fabrications. After you receive the chips from MOSIS, you will need to do some test and submit an on-line report back to MOSIS. |
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